[llvm] [PowerPC] don't eliminate the signext if the input is zero extended (PR #84419)

[Chen Zheng via llvm-commits]

================
@@ -1041,6 +1041,11 @@ bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
   case PPC::EXTSW_32:
   case PPC::EXTSW_32_64:
     SrcReg = MI.getOperand(1).getReg();
+    // On 64-bit targets, extension can not be eliminated if the input is zero
+    // extended. The input before zero extention may be a negative value.
+    if (Subtarget.isPPC64() &&
+        isZeroExtended(SrcReg, &MI.getMF()->getRegInfo()))
+      return false;
     DstReg = MI.getOperand(0).getReg();
     SubIdx = PPC::sub_32;
----------------
chenzheng1030 wrote:

> IIUC, this transformation is incorrect when SrcReg is i16 or narrower. If SrcReg is i32, this transforamtion is still valid.

There will be no i16 at this instremit phase(after isel).

The bug is in the description
```
    t39: i64 = LDtoc<Mem:(load (s64) from got)> TargetGlobalAddress:i64<ptr @b> 0, Register:i64 $x2
  t4: i32,ch = LWZ<Mem:(dereferenceable load (s32) from @b, !tbaa !3)> TargetConstant:i64<0>, t39, t0
  t48: i64 = EXTSW_32_64 t4

        t7: ch = CopyToReg t0, Register:i64 %0, t48

  t2: i64,ch = CopyFromReg t0, Register:i64 %0
          t5: i32 = EXTRACT_SUBREG t2, TargetConstant:i32<1>
```
to:

```
  %3:gprc = LWZ 0, killed %2:g8rc_and_g8rc_nox0 :: (dereferenceable load (s32) from @b, !tbaa !3)
  %24:gprc = COPY %3:gprc
```

The specific thing on PPC is `EXTSW_32_64(LWZ)`. If `LWZ` loads a negative value. Then higher 32bit of the  `EXTSW_32_64` result will be all 1 instead of 0.

(Due to such specialness on PPC, the optimization is guarded under a target hook `TII->isCoalescableExtInstr()`.)

After the `COPY` optimization:
```
%3:gprc = LWZ 0, killed %2:g8rc_and_g8rc_nox0 :: (dereferenceable load (s32) from @b, !tbaa !3)
`%24:gprc  = COPY %3:gprc`, the higher 32-bit is undefined. In the final assembly, the higher 32-bits are all 0 from LWZ.
```

https://github.com/llvm/llvm-project/pull/84419