[llvm] [PowerPC] don't eliminate the signext if the input is zero extended (PR #84419)

[Kai Luo via llvm-commits]

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@@ -1041,6 +1041,11 @@ bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
   case PPC::EXTSW_32:
   case PPC::EXTSW_32_64:
     SrcReg = MI.getOperand(1).getReg();
+    // On 64-bit targets, extension can not be eliminated if the input is zero
+    // extended. The input before zero extention may be a negative value.
+    if (Subtarget.isPPC64() &&
+        isZeroExtended(SrcReg, &MI.getMF()->getRegInfo()))
+      return false;
     DstReg = MI.getOperand(0).getReg();
     SubIdx = PPC::sub_32;
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bzEq wrote:

IIUC, this transformation is incorrect when `SrcReg` is i16 or narrower. If `SrcReg` is i32, this transforamtion is still valid.

https://github.com/llvm/llvm-project/pull/84419