[llvm] [RISCV][NFC] Simplify RISCVInstrInfo::copyPhysReg (PR #84139)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 6 22:48:57 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84139
>From 033f79559c4e7e4952f200fce8c95b5e61be3dee Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Wed, 6 Mar 2024 16:36:31 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
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Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.4
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 154 ++++++-----------------
1 file changed, 40 insertions(+), 114 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index ef0d7cbc835d0d..64b51a87953da0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -473,122 +473,48 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
return;
}
- if (RISCV::FPR32RegClass.contains(DstReg) &&
- RISCV::GPRRegClass.contains(SrcReg)) {
- BuildMI(MBB, MBBI, DL, get(RISCV::FMV_W_X), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
-
- if (RISCV::GPRRegClass.contains(DstReg) &&
- RISCV::FPR32RegClass.contains(SrcReg)) {
- BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_W), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
-
- if (RISCV::FPR64RegClass.contains(DstReg) &&
- RISCV::GPRRegClass.contains(SrcReg)) {
- assert(STI.getXLen() == 64 && "Unexpected GPR size");
- BuildMI(MBB, MBBI, DL, get(RISCV::FMV_D_X), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
-
- if (RISCV::GPRRegClass.contains(DstReg) &&
- RISCV::FPR64RegClass.contains(SrcReg)) {
- assert(STI.getXLen() == 64 && "Unexpected GPR size");
- BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_D), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
+#define COPY_FROM_TO(FROM, TO, OPC) \
+ do { \
+ if (FROM.contains(SrcReg) && TO.contains(DstReg)) { \
+ BuildMI(MBB, MBBI, DL, get(OPC), DstReg) \
+ .addReg(SrcReg, getKillRegState(KillSrc)); \
+ return; \
+ } \
+ } while (0)
+
+ COPY_FROM_TO(RISCV::GPRRegClass, RISCV::FPR32RegClass, RISCV::FMV_W_X);
+ COPY_FROM_TO(RISCV::FPR32RegClass, RISCV::GPRRegClass, RISCV::FMV_X_W);
+ COPY_FROM_TO(RISCV::GPRRegClass, RISCV::FPR64RegClass, RISCV::FMV_D_X);
+ COPY_FROM_TO(RISCV::FPR64RegClass, RISCV::GPRRegClass, RISCV::FMV_X_D);
+
+#define RVV_COPY_IMPL(REG_CLASS, LMUL, NF) \
+ do { \
+ if (RISCV::REG_CLASS.contains(DstReg, SrcReg)) { \
+ copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, \
+ RISCV::VMV##LMUL##R_V, NF); \
+ return; \
+ } \
+ } while (0)
+#define RVV_COPY(LMUL) RVV_COPY_IMPL(VRM##LMUL##RegClass, LMUL, 1)
+#define RVV_COPY_SEGMENT(LMUL, NF) \
+ RVV_COPY_IMPL(VRN##NF##M##LMUL##RegClass, LMUL, NF)
// VR->VR copies.
- if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V);
- return;
- }
-
- if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V);
- return;
- }
-
- if (RISCV::VRM4RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V);
- return;
- }
-
- if (RISCV::VRM8RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV8R_V);
- return;
- }
-
- if (RISCV::VRN2M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
- /*NF=*/2);
- return;
- }
-
- if (RISCV::VRN2M2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
- /*NF=*/2);
- return;
- }
-
- if (RISCV::VRN2M4RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV4R_V,
- /*NF=*/2);
- return;
- }
-
- if (RISCV::VRN3M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
- /*NF=*/3);
- return;
- }
-
- if (RISCV::VRN3M2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
- /*NF=*/3);
- return;
- }
-
- if (RISCV::VRN4M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
- /*NF=*/4);
- return;
- }
-
- if (RISCV::VRN4M2RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV2R_V,
- /*NF=*/4);
- return;
- }
-
- if (RISCV::VRN5M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
- /*NF=*/5);
- return;
- }
-
- if (RISCV::VRN6M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
- /*NF=*/6);
- return;
- }
-
- if (RISCV::VRN7M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
- /*NF=*/7);
- return;
- }
-
- if (RISCV::VRN8M1RegClass.contains(DstReg, SrcReg)) {
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RISCV::VMV1R_V,
- /*NF=*/8);
- return;
- }
+ RVV_COPY_IMPL(VRRegClass, 1, 1);
+ RVV_COPY(2);
+ RVV_COPY(4);
+ RVV_COPY(8);
+ RVV_COPY_SEGMENT(1, 2);
+ RVV_COPY_SEGMENT(2, 2);
+ RVV_COPY_SEGMENT(4, 2);
+ RVV_COPY_SEGMENT(1, 3);
+ RVV_COPY_SEGMENT(2, 3);
+ RVV_COPY_SEGMENT(1, 4);
+ RVV_COPY_SEGMENT(2, 4);
+ RVV_COPY_SEGMENT(1, 5);
+ RVV_COPY_SEGMENT(1, 6);
+ RVV_COPY_SEGMENT(1, 7);
+ RVV_COPY_SEGMENT(1, 8);
llvm_unreachable("Impossible reg-to-reg copy");
}
>From 52eeef17898f3bfab3a6155b5b30b28c6af38fa7 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: Thu, 7 Mar 2024 14:48:47 +0800
Subject: [PATCH 2/2] Only RVV copy and rework it
Created using spr 1.3.4
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 80 ++++++++++++++----------
1 file changed, 46 insertions(+), 34 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 64b51a87953da0..e4656c5b97a099 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -473,48 +473,60 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
return;
}
-#define COPY_FROM_TO(FROM, TO, OPC) \
- do { \
- if (FROM.contains(SrcReg) && TO.contains(DstReg)) { \
- BuildMI(MBB, MBBI, DL, get(OPC), DstReg) \
- .addReg(SrcReg, getKillRegState(KillSrc)); \
- return; \
- } \
- } while (0)
+ if (RISCV::FPR32RegClass.contains(DstReg) &&
+ RISCV::GPRRegClass.contains(SrcReg)) {
+ BuildMI(MBB, MBBI, DL, get(RISCV::FMV_W_X), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
+
+ if (RISCV::GPRRegClass.contains(DstReg) &&
+ RISCV::FPR32RegClass.contains(SrcReg)) {
+ BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_W), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
- COPY_FROM_TO(RISCV::GPRRegClass, RISCV::FPR32RegClass, RISCV::FMV_W_X);
- COPY_FROM_TO(RISCV::FPR32RegClass, RISCV::GPRRegClass, RISCV::FMV_X_W);
- COPY_FROM_TO(RISCV::GPRRegClass, RISCV::FPR64RegClass, RISCV::FMV_D_X);
- COPY_FROM_TO(RISCV::FPR64RegClass, RISCV::GPRRegClass, RISCV::FMV_X_D);
+ if (RISCV::FPR64RegClass.contains(DstReg) &&
+ RISCV::GPRRegClass.contains(SrcReg)) {
+ assert(STI.getXLen() == 64 && "Unexpected GPR size");
+ BuildMI(MBB, MBBI, DL, get(RISCV::FMV_D_X), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
+
+ if (RISCV::GPRRegClass.contains(DstReg) &&
+ RISCV::FPR64RegClass.contains(SrcReg)) {
+ assert(STI.getXLen() == 64 && "Unexpected GPR size");
+ BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_D), DstReg)
+ .addReg(SrcReg, getKillRegState(KillSrc));
+ return;
+ }
-#define RVV_COPY_IMPL(REG_CLASS, LMUL, NF) \
+#define RVV_COPY(REG_CLASS, OPC, NF) \
do { \
- if (RISCV::REG_CLASS.contains(DstReg, SrcReg)) { \
- copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, \
- RISCV::VMV##LMUL##R_V, NF); \
+ if (REG_CLASS.contains(DstReg, SrcReg)) { \
+ copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, OPC, NF); \
return; \
} \
} while (0)
-#define RVV_COPY(LMUL) RVV_COPY_IMPL(VRM##LMUL##RegClass, LMUL, 1)
-#define RVV_COPY_SEGMENT(LMUL, NF) \
- RVV_COPY_IMPL(VRN##NF##M##LMUL##RegClass, LMUL, NF)
// VR->VR copies.
- RVV_COPY_IMPL(VRRegClass, 1, 1);
- RVV_COPY(2);
- RVV_COPY(4);
- RVV_COPY(8);
- RVV_COPY_SEGMENT(1, 2);
- RVV_COPY_SEGMENT(2, 2);
- RVV_COPY_SEGMENT(4, 2);
- RVV_COPY_SEGMENT(1, 3);
- RVV_COPY_SEGMENT(2, 3);
- RVV_COPY_SEGMENT(1, 4);
- RVV_COPY_SEGMENT(2, 4);
- RVV_COPY_SEGMENT(1, 5);
- RVV_COPY_SEGMENT(1, 6);
- RVV_COPY_SEGMENT(1, 7);
- RVV_COPY_SEGMENT(1, 8);
+ RVV_COPY(RISCV::VRRegClass, RISCV::VMV1R_V, 1);
+ RVV_COPY(RISCV::VRM2RegClass, RISCV::VMV2R_V, 1);
+ RVV_COPY(RISCV::VRM4RegClass, RISCV::VMV4R_V, 1);
+ RVV_COPY(RISCV::VRM8RegClass, RISCV::VMV8R_V, 1);
+ RVV_COPY(RISCV::VRN2M1RegClass, RISCV::VMV1R_V, 2);
+ RVV_COPY(RISCV::VRN2M2RegClass, RISCV::VMV2R_V, 2);
+ RVV_COPY(RISCV::VRN2M4RegClass, RISCV::VMV4R_V, 2);
+ RVV_COPY(RISCV::VRN3M1RegClass, RISCV::VMV1R_V, 3);
+ RVV_COPY(RISCV::VRN3M2RegClass, RISCV::VMV2R_V, 3);
+ RVV_COPY(RISCV::VRN4M1RegClass, RISCV::VMV1R_V, 4);
+ RVV_COPY(RISCV::VRN4M2RegClass, RISCV::VMV2R_V, 4);
+ RVV_COPY(RISCV::VRN5M1RegClass, RISCV::VMV1R_V, 5);
+ RVV_COPY(RISCV::VRN6M1RegClass, RISCV::VMV1R_V, 6);
+ RVV_COPY(RISCV::VRN7M1RegClass, RISCV::VMV1R_V, 7);
+ RVV_COPY(RISCV::VRN8M1RegClass, RISCV::VMV1R_V, 8);
llvm_unreachable("Impossible reg-to-reg copy");
}
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