[llvm] [RISCV][NFC] Simplify RISCVInstrInfo::copyPhysReg (PR #84139)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 6 09:07:06 PST 2024
================
@@ -473,122 +473,48 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
return;
}
- if (RISCV::FPR32RegClass.contains(DstReg) &&
- RISCV::GPRRegClass.contains(SrcReg)) {
- BuildMI(MBB, MBBI, DL, get(RISCV::FMV_W_X), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
-
- if (RISCV::GPRRegClass.contains(DstReg) &&
- RISCV::FPR32RegClass.contains(SrcReg)) {
- BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_W), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
-
- if (RISCV::FPR64RegClass.contains(DstReg) &&
- RISCV::GPRRegClass.contains(SrcReg)) {
- assert(STI.getXLen() == 64 && "Unexpected GPR size");
- BuildMI(MBB, MBBI, DL, get(RISCV::FMV_D_X), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
-
- if (RISCV::GPRRegClass.contains(DstReg) &&
- RISCV::FPR64RegClass.contains(SrcReg)) {
- assert(STI.getXLen() == 64 && "Unexpected GPR size");
- BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_D), DstReg)
- .addReg(SrcReg, getKillRegState(KillSrc));
- return;
- }
+#define COPY_FROM_TO(FROM, TO, OPC) \
+ do { \
+ if (FROM.contains(SrcReg) && TO.contains(DstReg)) { \
+ BuildMI(MBB, MBBI, DL, get(OPC), DstReg) \
+ .addReg(SrcReg, getKillRegState(KillSrc)); \
+ return; \
+ } \
+ } while (0)
+
+ COPY_FROM_TO(RISCV::GPRRegClass, RISCV::FPR32RegClass, RISCV::FMV_W_X);
+ COPY_FROM_TO(RISCV::FPR32RegClass, RISCV::GPRRegClass, RISCV::FMV_X_W);
+ COPY_FROM_TO(RISCV::GPRRegClass, RISCV::FPR64RegClass, RISCV::FMV_D_X);
+ COPY_FROM_TO(RISCV::FPR64RegClass, RISCV::GPRRegClass, RISCV::FMV_X_D);
----------------
topperc wrote:
Please undef the macros when you're done with them.
https://github.com/llvm/llvm-project/pull/84139
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