[llvm] [RISCV][NFC] Simplify RISCVInstrInfo::copyPhysReg (PR #84139)

[Luke Lau via llvm-commits]

================
@@ -473,122 +473,48 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     return;
   }
 
-  if (RISCV::FPR32RegClass.contains(DstReg) &&
-      RISCV::GPRRegClass.contains(SrcReg)) {
-    BuildMI(MBB, MBBI, DL, get(RISCV::FMV_W_X), DstReg)
-        .addReg(SrcReg, getKillRegState(KillSrc));
-    return;
-  }
-
-  if (RISCV::GPRRegClass.contains(DstReg) &&
-      RISCV::FPR32RegClass.contains(SrcReg)) {
-    BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_W), DstReg)
-        .addReg(SrcReg, getKillRegState(KillSrc));
-    return;
-  }
-
-  if (RISCV::FPR64RegClass.contains(DstReg) &&
-      RISCV::GPRRegClass.contains(SrcReg)) {
-    assert(STI.getXLen() == 64 && "Unexpected GPR size");
-    BuildMI(MBB, MBBI, DL, get(RISCV::FMV_D_X), DstReg)
-        .addReg(SrcReg, getKillRegState(KillSrc));
-    return;
-  }
-
-  if (RISCV::GPRRegClass.contains(DstReg) &&
-      RISCV::FPR64RegClass.contains(SrcReg)) {
-    assert(STI.getXLen() == 64 && "Unexpected GPR size");
-    BuildMI(MBB, MBBI, DL, get(RISCV::FMV_X_D), DstReg)
-        .addReg(SrcReg, getKillRegState(KillSrc));
-    return;
-  }
+#define COPY_FROM_TO(FROM, TO, OPC)                                            \
+  do {                                                                         \
+    if (FROM.contains(SrcReg) && TO.contains(DstReg)) {                        \
+      BuildMI(MBB, MBBI, DL, get(OPC), DstReg)                                 \
+          .addReg(SrcReg, getKillRegState(KillSrc));                           \
+      return;                                                                  \
+    }                                                                          \
+  } while (0)
+
+  COPY_FROM_TO(RISCV::GPRRegClass, RISCV::FPR32RegClass, RISCV::FMV_W_X);
+  COPY_FROM_TO(RISCV::FPR32RegClass, RISCV::GPRRegClass, RISCV::FMV_X_W);
+  COPY_FROM_TO(RISCV::GPRRegClass, RISCV::FPR64RegClass, RISCV::FMV_D_X);
+  COPY_FROM_TO(RISCV::FPR64RegClass, RISCV::GPRRegClass, RISCV::FMV_X_D);
+
+#define RVV_COPY_IMPL(REG_CLASS, LMUL, NF)                                     \
+  do {                                                                         \
+    if (RISCV::REG_CLASS.contains(DstReg, SrcReg)) {                           \
+      copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc,                \
+                        RISCV::VMV##LMUL##R_V, NF);                            \
+      return;                                                                  \
+    }                                                                          \
+  } while (0)
----------------
lukel97 wrote:

Alternatively we could just use a lambda. I think I would personally prefer to see the full `RISCV::VM2R_V` register/`VRN2M4RegClass` regclass spelt out.

https://github.com/llvm/llvm-project/pull/84139