[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Momchil Velikov via llvm-commits]

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@@ -3065,19 +3074,40 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
       std::swap(Reg1, Reg2);
       std::swap(FrameIdxReg1, FrameIdxReg2);
     }
+
+    unsigned PairRegs;
+    unsigned PnReg;
+    if (RPI.isPaired() && RPI.isScalable()) {
+      PairRegs = AArch64::Z0_Z1 + (RPI.Reg1 - AArch64::Z0);
+      if (!PtrueCreated) {
+        PtrueCreated = true;
+        // Any one of predicate-as-count will be free to use
+        // This can be replaced in the future if needed
+        PnReg = AArch64::PN8;
----------------
momchil-velikov wrote:

> It's not correct to blindly pick PN8 (P8) here. You can only clobber P8 if it is preserved by the preceding predicate callee-saves.

Good point. I guess I misread the AAPCS when I suggested to just pick an arbitrary register as scratch.

>  Alternatively, you could mark p8 as clobbered by the function so that the preceding callee-save spills will include p8.

I would prefer this solution.


https://github.com/llvm/llvm-project/pull/77665