[llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)

[Sander de Smalen via llvm-commits]

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@@ -1508,6 +1508,12 @@ static bool IsSVECalleeSave(MachineBasicBlock::iterator I) {
   switch (I->getOpcode()) {
   default:
     return false;
+  case AArch64::PTRUE_C_B:
+  case AArch64::LD1B_2Z_IMM:
+  case AArch64::ST1B_2Z_IMM:
+    assert((I->getMF()->getSubtarget<AArch64Subtarget>().hasSVE2p1() ||
+            I->getMF()->getSubtarget<AArch64Subtarget>().hasSME2()) &&
+           "Expected SME2 or SVE2.1 Targer Architecture.");
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sdesmalen-arm wrote:

nit: What's the idea behind having this assert in this place? I would expect other code (e.g. machine-verifier) to give a more user-friendly message about invalid instructions being emitted if the target doesn't have the right feature.

https://github.com/llvm/llvm-project/pull/77665