[llvm] [ARM][TableGen][MC] Change the ARM mnemonic operands to be optional for ASM parsing (PR #83436)

[Alfie Richards via llvm-commits]

================
@@ -608,12 +627,18 @@ struct MatchableInfo {
   void buildInstructionResultOperands();
   void buildAliasResultOperands(bool AliasConstraintsAreChecked);
 
-  /// operator< - Compare two matchables.
-  bool operator<(const MatchableInfo &RHS) const {
+  /// shouldBeMatchedBefore - Compare two matchables for ordering.
+  bool shouldBeMatchedBefore(const MatchableInfo &RHS,
+                             const CodeGenTarget &Target) const {
     // The primary comparator is the instruction mnemonic.
     if (int Cmp = Mnemonic.compare_insensitive(RHS.Mnemonic))
       return Cmp == -1;
 
+    // Sort by the resultant instuctions size, eg. for ARM instructions
+    // we must choose the smallest matching instruction.
+    if (Target.getPreferSmallerInstructions() && ResInstSize != RHS.ResInstSize)
+      return ResInstSize < RHS.ResInstSize;
+
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AlfieRichardsArm wrote:

It is my understanding this needs to be here for ARM. The architecture reference manual states: 
```
If neither .W nor .N is specified, the assembler can select either a 16-bit or 32-bit encoding. If both encoding
lengths are available, it must select a 16-bit encoding.
```
There are cases (such as thumb 1 instructions with a CCOut operand whereas thumb 2 doesnt) where the smaller instruction has more operands, so choosing that first would make this non-compliant. 

Either way this patch has been moved to https://github.com/llvm/llvm-project/pull/83587

https://github.com/llvm/llvm-project/pull/83436