[llvm] [RISCV] Prefer whole register loads and stores when VL=VLMAX (PR #75531)

Luke Lau via llvm-commits llvm-commits at lists.llvm.org
Sun Mar 3 23:50:11 PST 2024

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https://github.com/lukel97 edited https://github.com/llvm/llvm-project/pull/75531

Previous message: [llvm] [RISCV] Prefer whole register loads and stores when VL=VLMAX (PR #75531)
Next message: [llvm] 2640277 - [AArch64] Optimized generated assembly for bool to svbool_t conversions (#83001)
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