[llvm] [RISCV] Prefer whole register loads and stores when VL=VLMAX (PR #75531)

[Luke Lau via llvm-commits]

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@@ -9882,12 +9895,22 @@ RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
 
   MVT ContainerVT = getContainerForFixedLengthVector(VT);
 
-  SDValue VL = getVLOp(VT.getVectorNumElements(), ContainerVT, DL, DAG,
-                       Subtarget);
-
   SDValue NewValue =
       convertToScalableVector(ContainerVT, StoreVal, DAG, Subtarget);
 
+
+  // If we know the exact VLEN and our fixed length vector completely fills
+  // the container, use a whole register store instead.
+  const auto [MinVLMAX, MaxVLMAX] =
+      RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
+  if (MinVLMAX == MaxVLMAX && MinVLMAX == VT.getVectorNumElements() &&
+      getLMUL1VT(ContainerVT).bitsLE(ContainerVT))
+    return DAG.getStore(Store->getChain(), DL, NewValue, Store->getBasePtr(),
+                        Store->getMemOperand());
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lukel97 wrote:

The ultimate cause of the miscompile was due to a dodgy combine on ISD::STORE which incorrectly removed a load/store pair, assuming they didn't alias. There was nothing wrong in this PR, it just happened to trigger it by lowering to an ISD::STORE node instead of a llvm.riscv.vse intrinsic.

Coincidentally on the same day I began investigating this, https://github.com/llvm/llvm-project/pull/83017 was landed which fixes it.

I've added a test case here which illustrates it in more detail: 63725ab1196ac50509ad382fc12c56f6d8b5d874

https://github.com/llvm/llvm-project/pull/75531