[llvm] [X86] Improve transform for add-like nodes to `add` (PR #83691)

[via llvm-commits]

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@@ -5294,11 +5294,26 @@ void X86DAGToDAGISel::Select(SDNode *Node) {
       return;
     if (tryVPTERNLOG(Node))
       return;
-
     [[fallthrough]];
   case ISD::ADD:
     if (Opcode == ISD::ADD && matchBitExtract(Node))
       return;
+
+    // Convert addlike to add before final selection. Do this before we drop
+    // flags like `disjoint`.
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goldsteinn wrote:

in SelectCode i assume, when we get to `or_is_add` didn't have `disjoint` or `ISD::OR`.

https://github.com/llvm/llvm-project/pull/83691