[llvm] [X86] Improve transform for add-like nodes to `add` (PR #83691)

[via llvm-commits]

goldsteinn wrote:

> This seems like maybe the better patch
> 
> ```
> diff --git a/llvm/lib/Target/X86/X86InstrFragments.td b/llvm/lib/Target/X86/X86InstrFragments.td
> index adf527d72f5b..90ff0625e812 100644
> --- a/llvm/lib/Target/X86/X86InstrFragments.td
> +++ b/llvm/lib/Target/X86/X86InstrFragments.td
> @@ -676,12 +676,7 @@ def def32 : PatLeaf<(i32 GR32:$src), [{
>  
>  // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
>  def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
> -  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
> -    return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
> -
> -  KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
> -  KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
> -  return (~Known0.Zero & ~Known1.Zero) == 0;
> +  return CurDAG->isADDLike(SDValue(N, 0));
>  }]>;
>  
>  def shiftMask8 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{
> ```

I tried that, but it didn't work. What seemed to be the case is when we handle `or_is_add` we no longer have `ISD::OR`, but instead `X86ISD::OR{width}r{i/r}`

https://github.com/llvm/llvm-project/pull/83691