[llvm] [X86] Transform `(xor x, SIGN_BIT)` -> `(add x, SIGN_BIT)` 32 bit and smaller scalars (PR #83659)

[via llvm-commits]

goldsteinn wrote:

> > > > We already do some of this in X86DAGToDAGISel::matchAddressRecursively - maybe see why these cases weren't working there?
> > > 
> > > 
> > > I see:
> > > ```
> > >   case ISD::OR:
> > >   case ISD::XOR:
> > >     // See if we can treat the OR/XOR node as an ADD node.
> > >     if (!CurDAG->isADDLike(N))
> > >       break;
> > >     [[fallthrough]];
> > >   case ISD::ADD:
> > >     if (!matchAdd(N, AM, Depth))
> > >       return false;
> > >     break;
> > > ```
> > > 
> > > 
> > >     
> > >       
> > >     
> > > 
> > >       
> > >     
> > > 
> > >     
> > >   
> > > Which isn't quite the same, or is there another transform im missing?
> > > But it looks to me like whatever we are doing in `DAGToDag` isn't handling non-i32 types.
> > 
> > 
> > I tested a patch that transforms `IsAddLike` to `add` in `DAGToDAG` and it has a lot of changes. Im going to replace this impl with that.
> 
> Ahh, its a TD pattern:
> 
> ```
> let AddedComplexity = 5 in {
> def : Pat<(xor GR8:$src1, -128),
>           (ADD8ri GR8:$src1, -128)>;
> def : Pat<(xor GR16:$src1, -32768),
>           (ADD16ri GR16:$src1, -32768)>;
> def : Pat<(xor GR32:$src1, -2147483648),
>           (ADD32ri GR32:$src1, -2147483648)>;
> }
> ```

I created: https://github.com/llvm/llvm-project/pull/83691, although all the cases caught here end up being missed.

https://github.com/llvm/llvm-project/pull/83659