[llvm] [RISCV] Move V0 to the end of register allocation order (PR #82967)

[Philip Reames via llvm-commits]

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@@ -510,17 +510,21 @@ defvar VM8VTs = [vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
 
 def VR : VReg<!listconcat(VM1VTs, VMaskVTs),
               (add (sequence "V%u", 8, 31),
-                   (sequence "V%u", 0, 7)), 1>;
+                   // Reverse the order so that we don't kill too much
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preames wrote:

Revise the comment to: Reverse the order so that we don't needlessly prevent allocation of higher lmul register groups while still putting v0 last in the allocation order.

https://github.com/llvm/llvm-project/pull/82967