[llvm] Silence potential overflow warning (PR #83272)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 28 07:13:57 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Martin Wehking (MartinWehking)
<details>
<summary>Changes</summary>
Cast Offset variable to int64_t type directly inside a multiplication and function call to utilize 64-bit arithmetic.
Ensure that the multiplication will not overflow.
A static analyzer warned about this since the function expects a 64-bit argument, but the multiplication is evaluated inside a 32-bit context.
---
Full diff: https://github.com/llvm/llvm-project/pull/83272.diff
1 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (+2-2)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 3664535b325997..2f204dc9fac888 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1752,12 +1752,12 @@ void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index,
unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
: AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false,
- FrameReg, Offset * SB.EltSize, MMO, SB.RS);
+ FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
} else {
unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
: AMDGPU::BUFFER_STORE_DWORD_OFFSET;
buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,
- FrameReg, Offset * SB.EltSize, MMO, SB.RS);
+ FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
// This only ever adds one VGPR spill
SB.MFI.addToSpilledVGPRs(1);
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/83272
More information about the llvm-commits
mailing list