[llvm] Silence potential overflow warning (PR #83272)

[Martin Wehking via llvm-commits]

https://github.com/MartinWehking created https://github.com/llvm/llvm-project/pull/83272

Cast Offset variable to int64_t type directly inside a multiplication and function call to utilize 64-bit arithmetic.

Ensure that the multiplication will not overflow.

A static analyzer warned about this since the function expects a 64-bit argument, but the multiplication is evaluated inside a 32-bit context.

>From b7b7f0b856db75c4f63007d7e32c45dd33b24f1e Mon Sep 17 00:00:00 2001
From: Martin Wehking <martin.wehking at codeplay.com>
Date: Wed, 28 Feb 2024 15:04:23 +0000
Subject: [PATCH] Silence potential overflow warning

Cast Offset variable to int64_t type directly inside a multiplication
and function call to utilize 64-bit arithmetic.

Ensure that the multiplication will not overflow.

A static analyzer warned about this since the function expects a
64-bit argument, but the multiplication is evaluated inside a
32-bit context.
---
 llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 3664535b325997..2f204dc9fac888 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1752,12 +1752,12 @@ void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index,
     unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
                                           : AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
     buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false,
-                        FrameReg, Offset * SB.EltSize, MMO, SB.RS);
+                        FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
   } else {
     unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
                                           : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
     buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,
-                        FrameReg, Offset * SB.EltSize, MMO, SB.RS);
+                        FrameReg, (int64_t)Offset * SB.EltSize, MMO, SB.RS);
     // This only ever adds one VGPR spill
     SB.MFI.addToSpilledVGPRs(1);
   }