[llvm] [AArch64] Support scalable offsets with isLegalAddressingMode (PR #83255)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 28 04:03:00 PST 2024
github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff 686ec7c2e9638d5b96d922886827a532d339856d 662cfe1429bbbedf287070f9d2b49bb56e874cd6 -- llvm/include/llvm/Analysis/TargetTransformInfo.h llvm/include/llvm/Analysis/TargetTransformInfoImpl.h llvm/include/llvm/CodeGen/BasicTTIImpl.h llvm/include/llvm/CodeGen/TargetLowering.h llvm/lib/Analysis/TargetTransformInfo.cpp llvm/lib/CodeGen/TargetLoweringBase.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/ARC/ARCISelLowering.cpp llvm/lib/Target/ARM/ARMISelLowering.cpp llvm/lib/Target/AVR/AVRISelLowering.cpp llvm/lib/Target/BPF/BPFISelLowering.cpp llvm/lib/Target/Hexagon/HexagonISelLowering.cpp llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp llvm/lib/Target/Mips/MipsISelLowering.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp llvm/lib/Target/PowerPC/PPCISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/XCore/XCoreISelLowering.cpp llvm/unittests/Target/AArch64/AddressingModes.cpp
``````````
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 0cfda08480..68158255bd 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -710,8 +710,7 @@ public:
/// TODO: Handle pre/postinc as well.
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
bool HasBaseReg, int64_t Scale,
- unsigned AddrSpace = 0,
- Instruction *I = nullptr,
+ unsigned AddrSpace = 0, Instruction *I = nullptr,
bool OffsetIsScalable = false) const;
/// Return true if LSR cost of C1 is lower than C2.
@@ -1840,8 +1839,7 @@ public:
virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
int64_t BaseOffset, bool HasBaseReg,
int64_t Scale, unsigned AddrSpace,
- Instruction *I,
- bool OffsetIsScalable) = 0;
+ Instruction *I, bool OffsetIsScalable) = 0;
virtual bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
const TargetTransformInfo::LSRCost &C2) = 0;
virtual bool isNumRegsMajorCostOfLSR() = 0;
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 4bb0255c2b..70c41f7b5a 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -333,8 +333,8 @@ public:
}
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
- bool HasBaseReg, int64_t Scale,
- unsigned AddrSpace, Instruction *I = nullptr,
+ bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
+ Instruction *I = nullptr,
bool OffsetIsScalable = false) {
TargetLoweringBase::AddrMode AM;
AM.BaseGV = BaseGV;
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 90bfa2983d..c4dd714930 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2696,7 +2696,7 @@ public:
int64_t BaseOffs = 0;
bool HasBaseReg = false;
int64_t Scale = 0;
- bool OffsetIsScalable = false;
+ bool OffsetIsScalable = false;
AddrMode() = default;
};
``````````
</details>
https://github.com/llvm/llvm-project/pull/83255
More information about the llvm-commits
mailing list