[llvm] [AArch64] Optimized generated assembly for bool to svbool_t conversions (PR #83001)

[Paul Walker via llvm-commits]

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@@ -269,13 +269,15 @@ static bool isMergePassthruOpcode(unsigned Opc) {
 
 // Returns true if inactive lanes are known to be zeroed by construction.
 static bool isZeroingInactiveLanes(SDValue Op) {
+  // Skip bitcasts nodes
+  while (Op->getOpcode() == ISD::BITCAST)
+    Op = Op->getOperand(0);
+    
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paulwalker-arm wrote:

Is this necessary?  The function is specific to predicate vectors so I'm not sure what bit casts are likely to be present.

https://github.com/llvm/llvm-project/pull/83001