[llvm] [RISCV] Move V0 to the end of register allocation order (PR #82967)

[Brandon Wu via llvm-commits]

4vtomat wrote:

> @4vtomat Would this change impact Vector Calling Convention?

It doesn't matter for now since vector calling convention uses the order of these arrays: [link](https://github.com/llvm/llvm-project/blob/3356818eed3224c50012f8ed2bfa046f2bc8e154/llvm/lib/Target/RISCV/RISCVISelLowering.cpp#L17787-L17796)~

https://github.com/llvm/llvm-project/pull/82967