[llvm] [RISCV] Move V0 to the end of register allocation order (PR #82967)

Wang Pengcheng via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 26 00:43:53 PST 2024

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wangpc-pp wrote:

@4vtomat Would this change impact Vector Calling Convention?

https://github.com/llvm/llvm-project/pull/82967

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