[llvm] [TTI][RISCV]Improve costs for whole vector reg extract/insert. (PR #80164)

[Luke Lau via llvm-commits]

================
@@ -432,12 +444,19 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
     // must be implemented here.
     break;
   case TTI::SK_ExtractSubvector:
+    // Extract at zero is always a subregister extract
+    if (Index == 0)
+      return TTI::TCC_Free;
+
     // Example sequence:
     // vsetivli     zero, 4, e8, mf2, tu, ma (ignored)
     // vslidedown.vi  v8, v9, 2
     return LT.first *
            getRISCVInstructionCost(RISCV::VSLIDEDOWN_VI, LT.second, CostKind);
   case TTI::SK_InsertSubvector:
+    if (Index == 0 && any_of(Args, UndefValue::classof))
----------------
lukel97 wrote:

Yeah, I think that's what RISCVISelLowering currently does.

My concern was that it Args could be arbitrary inserts from possibly the same vector, e.g.

```llvm
shufflevector <8 x i32> %x, <8 x i32> poison, <4 x i32> <i32 0, i32, 1, i32 4, i32 5>
```
Would be an insert of the second half of %x into the first half of %x.

But I took a closer look and I don't think TTI::SK_InsertSubvector is actually used in this case. `ShuffleVectorInst::isInsertSubvectorMask` only seems to detect inserts of operand 2 into operand 1, so I think the args can be treated as vector and subvector respectively. 

https://github.com/llvm/llvm-project/pull/80164