[llvm] [RISCV] Remove X0 handling from RISCVInstrInfo::optimizeCondBranch. (PR #81931)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

This was trying to rewrite a branch that uses X0 to a branch that uses a register produced by LI of 1 or -1. Using X0 is free so there isn't no reason to rewrite it. Doing so would just extend the live range of the other register increasing register pressure.

In practice this might not have triggered often because we were calling MRI.hasOneUse on X0. I'm not sure what the returns for a physical reigster.

---
Full diff: https://github.com/llvm/llvm-project/pull/81931.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+1-7) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 225a9db8f3ee11..62a44785321398 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1211,13 +1211,7 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
     if (!Op.isReg())
       return false;
     Register Reg = Op.getReg();
-    if (Reg == RISCV::X0) {
-      Imm = 0;
-      return true;
-    }
-    if (!Reg.isVirtual())
-      return false;
-    return isLoadImm(MRI.getVRegDef(Op.getReg()), Imm);
+    return Reg.isVirtual() && isLoadImm(MRI.getVRegDef(Reg), Imm);
   };
 
   MachineOperand &LHS = MI.getOperand(0);

``````````

</details>


https://github.com/llvm/llvm-project/pull/81931