[llvm] [RISCV] Remove X0 handling from RISCVInstrInfo::optimizeCondBranch. (PR #81931)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 15 14:14:13 PST 2024


https://github.com/topperc created https://github.com/llvm/llvm-project/pull/81931

This was trying to rewrite a branch that uses X0 to a branch that uses a register produced by LI of 1 or -1. Using X0 is free so there isn't no reason to rewrite it. Doing so would just extend the live range of the other register increasing register pressure.

In practice this might not have triggered often because we were calling MRI.hasOneUse on X0. I'm not sure what the returns for a physical reigster.

>From ff9c77d9691e20ef223bf271df8b864368563be0 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 15 Feb 2024 14:09:45 -0800
Subject: [PATCH] [RISCV] Remove X0 handling from
 RISCVInstrInfo::optimizeCondBranch.

This was trying to rewrite a branch that uses X0 to a branch that
uses a register produced by LI of 1 or -1. Using X0 is free so there
isn't no reason to rewrite it. Doing so would just extend the live
range of the other register increasing register pressure.

In practice this might not have triggered often because we were
calling MRI.hasOneUse on X0. I'm not sure what the returns for a
physical reigster.
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 225a9db8f3ee11..62a44785321398 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1211,13 +1211,7 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
     if (!Op.isReg())
       return false;
     Register Reg = Op.getReg();
-    if (Reg == RISCV::X0) {
-      Imm = 0;
-      return true;
-    }
-    if (!Reg.isVirtual())
-      return false;
-    return isLoadImm(MRI.getVRegDef(Op.getReg()), Imm);
+    return Reg.isVirtual() && isLoadImm(MRI.getVRegDef(Reg), Imm);
   };
 
   MachineOperand &LHS = MI.getOperand(0);



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