[llvm] [TargetLowering] Emit SIGN_EXTEND_INREG instead of shift pair from optimizeSetCCOfSignedTruncationCheck. (PR #81785)

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git-clang-format --diff 9b80ab4332bbe336ab8b9f2082eadf6b8d223150 f0a6ffcdd0b4f95f1382c349469865dab09a496b -- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 97a19be5d7..cd2fb4b757 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -4083,12 +4083,12 @@ SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
   if (!DAG.getTargetLoweringInfo().shouldTransformSignedTruncationCheck(
           XVT, KeptBits))
     return SDValue();
-Emit as
-  // Unfold into:  (sext_inreg(%x) cond %x
-  // Where 'cond' will be either 'eq' or 'ne'.
-  SDValue SExtInReg = DAG.getNode(
-      ISD::SIGN_EXTEND_INREG, DL, XVT, X,
-      DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), KeptBits)));
+  Emit as
+      // Unfold into:  (sext_inreg(%x) cond %x
+      // Where 'cond' will be either 'eq' or 'ne'.
+      SDValue SExtInReg = DAG.getNode(
+          ISD::SIGN_EXTEND_INREG, DL, XVT, X,
+          DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), KeptBits)));
   return DAG.getSetCC(DL, SCCVT, SExtInReg, X, NewCond);
 }
 

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https://github.com/llvm/llvm-project/pull/81785