[llvm] [TargetLowering] Emit SIGN_EXTEND_INREG instead of shift pair from optimizeSetCCOfSignedTruncationCheck. (PR #81785)

[Craig Topper via llvm-commits]

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/81785

>From b1fbe46b2658996a2ae77d28ad20966455892a69 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Wed, 14 Feb 2024 12:48:59 -0800
Subject: [PATCH 1/2] [TargetLowering] Emit SIGN_EXTEND_INREG instead of shift
 pair from optimizeSetCCOfSignedTruncationCheck.

This is our canonical form of shift pair before op legalization
so DAG combiner will probably create it anyway. If it isn't legal
LegalizeDAG will get expand to shifts later.
---
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index a4987de43779af..008db00f886b5a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -4084,17 +4084,12 @@ SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
           XVT, KeptBits))
     return SDValue();
 
-  const unsigned MaskedBits = XVT.getSizeInBits() - KeptBits;
-  assert(MaskedBits > 0 && MaskedBits < XVT.getSizeInBits() && "unreachable");
-
-  // Unfold into:  ((%x << C) a>> C) cond %x
+  // Unfold into:  (sext_inreg(X) cond %x
   // Where 'cond' will be either 'eq' or 'ne'.
-  SDValue ShiftAmt = DAG.getConstant(MaskedBits, DL, XVT);
-  SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt);
-  SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt);
-  SDValue T2 = DAG.getSetCC(DL, SCCVT, T1, X, NewCond);
-
-  return T2;
+  SDValue SExtInReg = DAG.getNode(
+      ISD::SIGN_EXTEND_INREG, DL, XVT, X,
+      DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), KeptBits)));
+  return DAG.getSetCC(DL, SCCVT, SExtInReg, X, NewCond);
 }
 
 // (X & (C l>>/<< Y)) ==/!= 0  -->  ((X <</l>> Y) & C) ==/!= 0

>From f0a6ffcdd0b4f95f1382c349469865dab09a496b Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 15 Feb 2024 08:13:13 -0800
Subject: [PATCH 2/2] fixup! fix typo in comment

---
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 008db00f886b5a..97a19be5d7ab38 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -4083,8 +4083,8 @@ SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
   if (!DAG.getTargetLoweringInfo().shouldTransformSignedTruncationCheck(
           XVT, KeptBits))
     return SDValue();
-
-  // Unfold into:  (sext_inreg(X) cond %x
+Emit as
+  // Unfold into:  (sext_inreg(%x) cond %x
   // Where 'cond' will be either 'eq' or 'ne'.
   SDValue SExtInReg = DAG.getNode(
       ISD::SIGN_EXTEND_INREG, DL, XVT, X,