[llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

[Luke Lau via llvm-commits]

lukel97 wrote:

> LMUL >=1 not enough for the second case, also need to check that the whole vector is insert, not, say, half of it.

But for llvm.vector.insert there is the constraint that all the subvec elements must be within bounds of the vector, and for scalable vectors the index at which it is inserted is scaled by vscale.

So if the subvector is LMUL >=1 it shouldn't be possible for only half of it be inserted, since it won't be truncated and the index will be a multiple of an LMUL1 register boundary.

This is separate from the exact VLEN fixed vector case in the original version of this PR though, we can leave it for a future patch.

https://github.com/llvm/llvm-project/pull/80164