[llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

[Alexey Bataev via llvm-commits]

alexey-bataev wrote:

> #81751 handles both fixed and scalable vectors from the looks of things. I wonder if it's possible to have this patch handle the whole reg extract/insert case for scalable vectors too, if we move the logic into the scalable part below the fixed vector switch? Any scalable vector extract/insert should be free if both the vector and subvector are >= LMUL 1.

Not sure that insert subvector should be free. It can be free, if either the second vector is undef or inserting the whole vector. LMUL >=1 not enough for the second case, also need to check that the whole vector is insert, not, say, half of it.

https://github.com/llvm/llvm-project/pull/80164