[llvm] [RFC] implement convergence control in MIR using SelectionDAG (PR #71785)

[Sameer Sahasrabuddhe via llvm-commits]

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@@ -285,6 +285,27 @@ Register InstrEmitter::getVR(SDValue Op,
   return I->second;
 }
 
+static bool isConvergenceCtrlIntrinsic(SDValue Op) {
+  if (Op->isMachineOpcode()) {
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ssahasra wrote:

@arsenm the review already has your approval, but I don't want to submit without closing all comments, especially this discussion about handling non-machine opcodes in instr-emitter.

https://github.com/llvm/llvm-project/pull/71785