[llvm] [RFC] implement convergence control in MIR using SelectionDAG (PR #71785)
Sameer Sahasrabuddhe via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 12 22:21:21 PST 2024
================
@@ -285,6 +285,27 @@ Register InstrEmitter::getVR(SDValue Op,
return I->second;
}
+static bool isConvergenceCtrlIntrinsic(SDValue Op) {
+ if (Op->isMachineOpcode()) {
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ssahasra wrote:
The emitter encounters ISD::CopyFromReg here. I am not so sure about making a special case for it. At least this way, the body of the function matches its name!
https://github.com/llvm/llvm-project/pull/71785
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