[llvm] [RISCV] Enable the TypePromotion pass from AArch64/ARM. (PR #81574)

[Craig Topper via llvm-commits]

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@@ -312,7 +315,10 @@ define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
 ; RV64-NEXT:    bnez a1, .LBB10_2
 ; RV64-NEXT:  # %bb.1: # %t
 ; RV64-NEXT:    li a0, 42
-; RV64-NEXT:  .LBB10_2: # %f
+; RV64-NEXT:    ret
+; RV64-NEXT:  .LBB10_2:
+; RV64-NEXT:    slli a0, a0, 48
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topperc wrote:

We moved the zext to the argument and updated both uses. Then in SelectionDAG we type legalize that to an AND. There's already an AND with 128 after it going to the compare so we decide we don't need the other AND on that path. That leaves the AND only serving the return which doesn't care about the upper bits.

Seems like there was no reason to move the zext for this case.

https://github.com/llvm/llvm-project/pull/81574