[llvm] [RISCV] Enable the TypePromotion pass from AArch64/ARM. (PR #81574)

[Philip Reames via llvm-commits]

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@@ -312,7 +315,10 @@ define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {
 ; RV64-NEXT:    bnez a1, .LBB10_2
 ; RV64-NEXT:  # %bb.1: # %t
 ; RV64-NEXT:    li a0, 42
-; RV64-NEXT:  .LBB10_2: # %f
+; RV64-NEXT:    ret
+; RV64-NEXT:  .LBB10_2:
+; RV64-NEXT:    slli a0, a0, 48
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preames wrote:

This delta is interesting and looks like a missed optimization.  After moving the zext, we appear to loose track of the fact that x was already used in the ABI, and thus should have the required properties for the return.  

https://github.com/llvm/llvm-project/pull/81574