[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[via llvm-commits]

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@@ -190,12 +190,17 @@ entry:
 define arm_aapcs_vfpcc <4 x i64> @sext32_0213_0ext(<8 x i32> %src1, i32 %src2) {
 ; CHECK-LABEL: sext32_0213_0ext:
 ; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .vsave {d8, d9}
+; CHECK-NEXT:    vpush {d8, d9}
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ostannard wrote:

The generated code for these tests has gotten longer, was this previously generating invalid code, or is this an unwanted side-effect of this pass?

https://github.com/llvm/llvm-project/pull/77770