[llvm] [RISCV] Exclude X1 and X5 from register scavenging for long branch. (PR #80215)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 12 09:17:56 PST 2024

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https://github.com/topperc closed https://github.com/llvm/llvm-project/pull/80215

Previous message: [llvm] [RISCV] Exclude X1 and X5 from register scavenging for long branch. (PR #80215)
Next message: [llvm] 673e5e3 - [Matrix] Add dedicated tests for transpose lifting.
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