[llvm] [RISCV] Exclude X1 and X5 from register scavenging for long branch. (PR #80215)

[Philip Reames via llvm-commits]

https://github.com/preames approved this pull request.

LGTM

(Thought I'd approved this after our previous exchange, but looks like I didn't.  Sorry for the delay.)

https://github.com/llvm/llvm-project/pull/80215