[llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

[Philip Reames via llvm-commits]

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@@ -326,6 +326,48 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
     switch (Kind) {
     default:
       break;
+    case TTI::SK_ExtractSubvector:
+      if (isa<FixedVectorType>(SubTp) &&
+          LT.second.getVectorElementType() != MVT::i1) {
+        unsigned SubTpRegs = getRegUsageForType(SubTp);
+        unsigned SubNumElems = NextPowerOf2(
+            divideCeil(SubTp->getElementCount().getFixedValue(), SubTpRegs));
+        // Whole vector extract - just the vector itself + (possible) vsetvli.
+        // TODO: consider adding the cost for vsetvli.
+        if (Index == 0 || (ST->getRealMaxVLen() == ST->getRealMinVLen() &&
+                           SubNumElems * LT.second.getScalarSizeInBits() ==
+                               ST->getRealMinVLen() &&
+                           Index % SubNumElems == 0))
+          return TTI::TCC_Free;
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preames wrote:

Style request - Please use early return for the Index == 0 case.

Once you do that, you can sink all of the other code inside a check for the exact VLEN and it should be much more clearly isolated. 

https://github.com/llvm/llvm-project/pull/80164