[llvm] [AArch64] Add FeatureFuseAdrpAdd for Ampere1/1A (PR #81293)

[Philipp Tomsich via llvm-commits]

https://github.com/ptomsich created https://github.com/llvm/llvm-project/pull/81293

Both Ampere1 and Ampere1A support fusion of ADRP+ADD.
This adds the missing feature to enable fusion-aware scheduling for this case.

>From 74652e90b4f1f8e1f648985dadfcae528aabc821 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich at vrull.eu>
Date: Thu, 8 Feb 2024 13:36:58 +0100
Subject: [PATCH] [AArch64] Add FeatureFuseAdrpAdd for Ampere1/1A

---
 llvm/lib/Target/AArch64/AArch64.td | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 02fb01caf7e801..155edaf7e194b2 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -1349,6 +1349,7 @@ def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1",
                                    "Ampere Computing Ampere-1 processors", [
                                    FeaturePostRAScheduler,
                                    FeatureFuseAES,
+                                   FeatureFuseAdrpAdd,
                                    FeatureAddrLSLFast,
                                    FeatureALULSLFast,
                                    FeatureAggressiveFMA,
@@ -1364,6 +1365,7 @@ def TuneAmpere1A : SubtargetFeature<"ampere1a", "ARMProcFamily", "Ampere1A",
                                     "Ampere Computing Ampere-1A processors", [
                                     FeaturePostRAScheduler,
                                     FeatureFuseAES,
+                                    FeatureFuseAdrpAdd,
                                     FeatureAddrLSLFast,
                                     FeatureALULSLFast,
                                     FeatureAggressiveFMA,