[llvm] [RISCV][GISEL] Add IRTranslation for insertelement with scalable vector type (PR #80377)

[Matt Arsenault via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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arsenm wrote:

And only i32. Should try with some i64s and non-constants 

https://github.com/llvm/llvm-project/pull/80377