[llvm] [RISCV][GISEL] Add IRTranslation for insertelement with scalable vector type (PR #80377)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 8 00:26:22 PST 2024
================
@@ -0,0 +1,1941 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
----------------
arsenm wrote:
And only i32. Should try with some i64s and non-constants
https://github.com/llvm/llvm-project/pull/80377
More information about the llvm-commits
mailing list