[llvm] f471420 - [X86] printExtend - add support for mask predicated instructions
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 5 08:24:01 PST 2024
Author: Simon Pilgrim
Date: 2024-02-05T16:23:15Z
New Revision: f4714204d0527269e037d85ed998a54678e3895f
URL: https://github.com/llvm/llvm-project/commit/f4714204d0527269e037d85ed998a54678e3895f
DIFF: https://github.com/llvm/llvm-project/commit/f4714204d0527269e037d85ed998a54678e3895f.diff
LOG: [X86] printExtend - add support for mask predicated instructions
Remove handling from EmitAnyX86InstComments and handle all VPMOVSX/VPMOVZX comments in addConstantComments now that we can generically handle the destination + mask register and shuffle mask comment
Added:
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
llvm/lib/Target/X86/X86MCInstLower.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
index e8a044b82eb80..9cc72d32d85f9 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
@@ -65,16 +65,6 @@ using namespace llvm;
CASE_AVX_INS_COMMON(Inst, Y, r##src) \
CASE_SSE_INS_COMMON(Inst, r##src)
-#define CASE_MASK_PMOVZX(Inst, src) \
- CASE_MASK_INS_COMMON(Inst, Z, r##src) \
- CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
- CASE_MASK_INS_COMMON(Inst, Z128, r##src)
-
-#define CASE_MASKZ_PMOVZX(Inst, src) \
- CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
- CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
- CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
-
#define CASE_UNPCK(Inst, src) \
CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
@@ -1317,9 +1307,6 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_PMOVZX(PMOVZXBW, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
- [[fallthrough]];
- CASE_MASK_PMOVZX(PMOVZXBW, m)
- CASE_MASKZ_PMOVZX(PMOVZXBW, m)
DecodeZeroExtendMask(8, 16, getRegOperandNumElts(MI, 16, 0), false,
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
@@ -1327,9 +1314,6 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_PMOVZX(PMOVZXBD, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
- [[fallthrough]];
- CASE_MASK_PMOVZX(PMOVZXBD, m)
- CASE_MASKZ_PMOVZX(PMOVZXBD, m)
DecodeZeroExtendMask(8, 32, getRegOperandNumElts(MI, 32, 0), false,
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
@@ -1337,9 +1321,6 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_PMOVZX(PMOVZXBQ, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
- [[fallthrough]];
- CASE_MASK_PMOVZX(PMOVZXBQ, m)
- CASE_MASKZ_PMOVZX(PMOVZXBQ, m)
DecodeZeroExtendMask(8, 64, getRegOperandNumElts(MI, 64, 0), false,
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
@@ -1347,9 +1328,6 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_PMOVZX(PMOVZXWD, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
- [[fallthrough]];
- CASE_MASK_PMOVZX(PMOVZXWD, m)
- CASE_MASKZ_PMOVZX(PMOVZXWD, m)
DecodeZeroExtendMask(16, 32, getRegOperandNumElts(MI, 32, 0), false,
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
@@ -1357,9 +1335,6 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_PMOVZX(PMOVZXWQ, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
- [[fallthrough]];
- CASE_MASK_PMOVZX(PMOVZXWQ, m)
- CASE_MASKZ_PMOVZX(PMOVZXWQ, m)
DecodeZeroExtendMask(16, 64, getRegOperandNumElts(MI, 64, 0), false,
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
@@ -1367,9 +1342,6 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
CASE_PMOVZX(PMOVZXDQ, r)
Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
- [[fallthrough]];
- CASE_MASK_PMOVZX(PMOVZXDQ, m)
- CASE_MASKZ_PMOVZX(PMOVZXDQ, m)
DecodeZeroExtendMask(32, 64, getRegOperandNumElts(MI, 64, 0), false,
ShuffleMask);
DestName = getRegName(MI->getOperand(0).getReg());
diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index c3038ccab4c44..3696ffb7f6999 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1422,9 +1422,8 @@ static void printDstRegisterName(raw_ostream &CS, const MachineInstr *MI,
// MASKZ: zmmX {%kY} {z}
if (X86II::isKMasked(MI->getDesc().TSFlags)) {
const MachineOperand &WriteMaskOp = MI->getOperand(SrcOpIdx - 1);
- CS << " {%";
- CS << X86ATTInstPrinter::getRegisterName(WriteMaskOp.getReg());
- CS << "}";
+ StringRef Mask = X86ATTInstPrinter::getRegisterName(WriteMaskOp.getReg());
+ CS << " {%" << Mask << "}";
if (!X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
CS << " {z}";
}
@@ -1604,16 +1603,15 @@ static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer,
static bool printExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
int SrcEltBits, int DstEltBits, bool IsSext) {
- auto *C = X86::getConstantFromPool(*MI, 1);
+ unsigned SrcIdx = getSrcIdx(MI, 1);
+ auto *C = X86::getConstantFromPool(*MI, SrcIdx);
if (C && C->getType()->getScalarSizeInBits() == unsigned(SrcEltBits)) {
if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
int NumElts = CDS->getNumElements();
std::string Comment;
raw_string_ostream CS(Comment);
-
- const MachineOperand &DstOp = MI->getOperand(0);
- CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
- CS << "[";
+ printDstRegisterName(CS, MI, SrcIdx);
+ CS << " = [";
for (int i = 0; i != NumElts; ++i) {
if (i != 0)
CS << ",";
@@ -1644,22 +1642,16 @@ static void printZeroExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
// We didn't find a constant load, fallback to a shuffle mask decode.
std::string Comment;
raw_string_ostream CS(Comment);
+ printDstRegisterName(CS, MI, getSrcIdx(MI, 1));
+ CS << " = ";
- const MachineOperand &DstOp = MI->getOperand(0);
- CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
-
+ SmallVector<int> Mask;
unsigned Width = getRegisterWidth(MI->getDesc().operands()[0]);
assert((Width % DstEltBits) == 0 && (DstEltBits % SrcEltBits) == 0 &&
"Illegal extension ratio");
- unsigned NumElts = Width / DstEltBits;
- unsigned Scale = DstEltBits / SrcEltBits;
- for (unsigned I = 0; I != NumElts; ++I) {
- if (I != 0)
- CS << ",";
- CS << "mem[" << I << "]";
- for (unsigned S = 1; S != Scale; ++S)
- CS << ",zero";
- }
+ DecodeZeroExtendMask(SrcEltBits, DstEltBits, Width / DstEltBits, false, Mask);
+ printShuffleMask(CS, "mem", "", Mask);
+
OutStreamer.AddComment(CS.str());
}
@@ -2010,16 +2002,22 @@ static void addConstantComments(const MachineInstr *MI,
printBroadcast(MI, OutStreamer, 64, 8);
break;
-#define MOVX_CASE(Prefix, Ext, Type, Suffix) \
- case X86::Prefix##PMOV##Ext##Type##Suffix##rm:
+#define MOVX_CASE(Prefix, Ext, Type, Suffix, Postfix) \
+ case X86::Prefix##PMOV##Ext##Type##Suffix##rm##Postfix:
#define CASE_MOVX_RM(Ext, Type) \
- MOVX_CASE(, Ext, Type, ) \
- MOVX_CASE(V, Ext, Type, ) \
- MOVX_CASE(V, Ext, Type, Y) \
- MOVX_CASE(V, Ext, Type, Z128) \
- MOVX_CASE(V, Ext, Type, Z256) \
- MOVX_CASE(V, Ext, Type, Z)
+ MOVX_CASE(, Ext, Type, , ) \
+ MOVX_CASE(V, Ext, Type, , ) \
+ MOVX_CASE(V, Ext, Type, Y, ) \
+ MOVX_CASE(V, Ext, Type, Z128, ) \
+ MOVX_CASE(V, Ext, Type, Z128, k ) \
+ MOVX_CASE(V, Ext, Type, Z128, kz ) \
+ MOVX_CASE(V, Ext, Type, Z256, ) \
+ MOVX_CASE(V, Ext, Type, Z256, k ) \
+ MOVX_CASE(V, Ext, Type, Z256, kz ) \
+ MOVX_CASE(V, Ext, Type, Z, ) \
+ MOVX_CASE(V, Ext, Type, Z, k ) \
+ MOVX_CASE(V, Ext, Type, Z, kz )
CASE_MOVX_RM(SX, BD)
printSignExtend(MI, OutStreamer, 8, 32);
More information about the llvm-commits
mailing list