[llvm] de9a873 - [X86] Split up getShuffleComment into printShuffleMask and printDstRegisterName helpers. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-02-05T16:23:15Z
New Revision: de9a87301aefda9538eab7fcd563cc6ceec44e0a

URL: https://github.com/llvm/llvm-project/commit/de9a87301aefda9538eab7fcd563cc6ceec44e0a
DIFF: https://github.com/llvm/llvm-project/commit/de9a87301aefda9538eab7fcd563cc6ceec44e0a.diff

LOG: [X86] Split up getShuffleComment into printShuffleMask and printDstRegisterName helpers. NFC.

This will allow us to easily use printDstRegisterName for other mask predicate destination registers, and printout shuffle masks from other instruction types.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86MCInstLower.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index aa060de3bfefd..c3038ccab4c44 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1412,51 +1412,33 @@ static unsigned getSrcIdx(const MachineInstr* MI, unsigned SrcIdx) {
   return SrcIdx;
 }
 
-static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
-                                     unsigned SrcOp2Idx, ArrayRef<int> Mask) {
-  std::string Comment;
-
-  // Compute the name for a register. This is really goofy because we have
-  // multiple instruction printers that could (in theory) use 
diff erent
-  // names. Fortunately most people use the ATT style (outside of Windows)
-  // and they actually agree on register naming here. Ultimately, this is
-  // a comment, and so its OK if it isn't perfect.
-  auto GetRegisterName = [](MCRegister Reg) -> StringRef {
-    return X86ATTInstPrinter::getRegisterName(Reg);
-  };
-
+static void printDstRegisterName(raw_ostream &CS, const MachineInstr *MI,
+                                 unsigned SrcOpIdx) {
   const MachineOperand &DstOp = MI->getOperand(0);
-  const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
-  const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
-
-  StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
-  StringRef Src1Name =
-      SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
-  StringRef Src2Name =
-      SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
-
-  // One source operand, fix the mask to print all elements in one span.
-  SmallVector<int, 8> ShuffleMask(Mask);
-  if (Src1Name == Src2Name)
-    for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
-      if (ShuffleMask[i] >= e)
-        ShuffleMask[i] -= e;
-
-  raw_string_ostream CS(Comment);
-  CS << DstName;
+  CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg());
 
   // Handle AVX512 MASK/MASXZ write mask comments.
   // MASK: zmmX {%kY}
   // MASKZ: zmmX {%kY} {z}
   if (X86II::isKMasked(MI->getDesc().TSFlags)) {
-    const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
-    CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
+    const MachineOperand &WriteMaskOp = MI->getOperand(SrcOpIdx - 1);
+    CS << " {%";
+    CS << X86ATTInstPrinter::getRegisterName(WriteMaskOp.getReg());
+    CS << "}";
     if (!X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
       CS << " {z}";
     }
   }
+}
 
-  CS << " = ";
+static void printShuffleMask(raw_ostream &CS, StringRef Src1Name,
+                             StringRef Src2Name, ArrayRef<int> Mask) {
+  // One source operand, fix the mask to print all elements in one span.
+  SmallVector<int, 8> ShuffleMask(Mask);
+  if (Src1Name == Src2Name)
+    for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
+      if (ShuffleMask[i] >= e)
+        ShuffleMask[i] -= e;
 
   for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
     if (i != 0)
@@ -1487,6 +1469,25 @@ static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
     CS << ']';
     --i; // For loop increments element #.
   }
+}
+
+static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
+                                     unsigned SrcOp2Idx, ArrayRef<int> Mask) {
+  std::string Comment;
+
+  const MachineOperand &SrcOp1 = MI->getOperand(SrcOp1Idx);
+  const MachineOperand &SrcOp2 = MI->getOperand(SrcOp2Idx);
+  StringRef Src1Name = SrcOp1.isReg()
+                           ? X86ATTInstPrinter::getRegisterName(SrcOp1.getReg())
+                           : "mem";
+  StringRef Src2Name = SrcOp2.isReg()
+                           ? X86ATTInstPrinter::getRegisterName(SrcOp2.getReg())
+                           : "mem";
+
+  raw_string_ostream CS(Comment);
+  printDstRegisterName(CS, MI, SrcOp1Idx);
+  CS << " = ";
+  printShuffleMask(CS, Src1Name, Src2Name, Mask);
   CS.flush();
 
   return Comment;