[llvm] [AMDGPU] Use correct number of bits needed for div/rem shrinking (PR #80622)

[via llvm-commits]

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@@ -1213,7 +1213,10 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem24(IRBuilder<> &Builder,
                                                 BinaryOperator &I, Value *Num,
                                                 Value *Den, bool IsDiv,
                                                 bool IsSigned) const {
-  int DivBits = getDivNumBits(I, Num, Den, 9, IsSigned);
+  unsigned SSBits = Num->getType()->getScalarSizeInBits();
+  // If Num bits <= 24, assume 0 signbits.
+  unsigned AtLeast = (SSBits <= 24) ? 0 : (SSBits - 24);
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choikwa wrote:

It depends on the type of Num. The faulty path arose from Num being i64 and AtLeast being 9, which meant that it permit integer dividend with up to 55 used bits to fall into path which assumed only 24. After this change, AtLeast should get 64-24=40 bits for i64 as Num's type, meaning only 24 used bits should now fall into expandDivRem24.

https://github.com/llvm/llvm-project/pull/80622