[llvm] [RISCV] Make X5 allocatable for JALR on CPUs without RAS (PR #78417)

[Wang Pengcheng via llvm-commits]

wangpc-pp wrote:

> > Ping for comments. :-)
> 
> If this didn't improve code size on llvm-test-suite, I think it just adds an extra configuration option for no benefit.
> 
> The ARM code specifically seems to use the feature to generate a longer code sequence for noreturn calls on CPUs that support RAS to avoid corrupting the predictor. So that seems different than this patch.

Yeah, make sense to me. We may investigate this again if it will be profitable in the future.


https://github.com/llvm/llvm-project/pull/78417