[llvm] 8ed046f - [RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 4 23:16:37 PST 2024
Author: Craig Topper
Date: 2024-02-04T23:15:58-08:00
New Revision: 8ed046fc15eae08a9cf7ec02974330d52606c663
URL: https://github.com/llvm/llvm-project/commit/8ed046fc15eae08a9cf7ec02974330d52606c663
DIFF: https://github.com/llvm/llvm-project/commit/8ed046fc15eae08a9cf7ec02974330d52606c663.diff
LOG: [RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
While working on -riscv-experimental-rv64-legal-i32, I noticed this
missed optimization in our current codegen.
This expands to SADDO/SSUBO+select while still in i32. These will
be type legalized individually.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/sadd_sat.ll
llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
llvm/test/CodeGen/RISCV/ssub_sat.ll
llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0d7fdfd9b9754..9f501ea7425de 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -282,6 +282,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
MVT::i32, Custom);
setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT},
MVT::i32, Custom);
+ if (!Subtarget.hasStdExtZbb())
+ setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, MVT::i32, Custom);
} else {
setOperationAction(ISD::SSUBO, MVT::i32, Custom);
if (Subtarget.hasStdExtZbb()) {
@@ -11879,6 +11881,13 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(expandAddSubSat(N, DAG));
return;
}
+ case ISD::SADDSAT:
+ case ISD::SSUBSAT: {
+ assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
+ "Unexpected custom legalisation");
+ Results.push_back(expandAddSubSat(N, DAG));
+ return;
+ }
case ISD::ABS: {
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
"Unexpected custom legalisation");
diff --git a/llvm/test/CodeGen/RISCV/sadd_sat.ll b/llvm/test/CodeGen/RISCV/sadd_sat.ll
index 8efeb3b1bb668..3dbaaeaf02b6c 100644
--- a/llvm/test/CodeGen/RISCV/sadd_sat.ll
+++ b/llvm/test/CodeGen/RISCV/sadd_sat.ll
@@ -27,19 +27,16 @@ define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
;
; RV64I-LABEL: func:
; RV64I: # %bb.0:
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 524288
-; RV64I-NEXT: addiw a2, a1, -1
-; RV64I-NEXT: bge a0, a2, .LBB0_3
+; RV64I-NEXT: add a2, a0, a1
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: beq a0, a2, .LBB0_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bge a1, a0, .LBB0_4
+; RV64I-NEXT: srli a0, a0, 31
+; RV64I-NEXT: li a1, 1
+; RV64I-NEXT: slli a1, a1, 31
+; RV64I-NEXT: xor a2, a0, a1
; RV64I-NEXT: .LBB0_2:
-; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB0_3:
-; RV64I-NEXT: mv a0, a2
-; RV64I-NEXT: blt a1, a2, .LBB0_2
-; RV64I-NEXT: .LBB0_4:
-; RV64I-NEXT: lui a0, 524288
+; RV64I-NEXT: sext.w a0, a2
; RV64I-NEXT: ret
;
; RV64IZbb-LABEL: func:
diff --git a/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
index 48b7ead5e7320..648ec8b30d389 100644
--- a/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
@@ -30,20 +30,15 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: mulw a1, a1, a2
+; RV64I-NEXT: addw a2, a0, a1
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 524288
-; RV64I-NEXT: addiw a2, a1, -1
-; RV64I-NEXT: bge a0, a2, .LBB0_3
+; RV64I-NEXT: beq a2, a0, .LBB0_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bge a1, a0, .LBB0_4
+; RV64I-NEXT: sraiw a0, a0, 31
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB0_3:
-; RV64I-NEXT: mv a0, a2
-; RV64I-NEXT: blt a1, a2, .LBB0_2
-; RV64I-NEXT: .LBB0_4:
-; RV64I-NEXT: lui a0, 524288
-; RV64I-NEXT: ret
;
; RV64IZbb-LABEL: func32:
; RV64IZbb: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/ssub_sat.ll b/llvm/test/CodeGen/RISCV/ssub_sat.ll
index 7732661dd1306..cc5cd76e913c6 100644
--- a/llvm/test/CodeGen/RISCV/ssub_sat.ll
+++ b/llvm/test/CodeGen/RISCV/ssub_sat.ll
@@ -27,19 +27,16 @@ define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
;
; RV64I-LABEL: func:
; RV64I: # %bb.0:
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 524288
-; RV64I-NEXT: addiw a2, a1, -1
-; RV64I-NEXT: bge a0, a2, .LBB0_3
+; RV64I-NEXT: sub a2, a0, a1
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: beq a0, a2, .LBB0_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bge a1, a0, .LBB0_4
+; RV64I-NEXT: srli a0, a0, 31
+; RV64I-NEXT: li a1, 1
+; RV64I-NEXT: slli a1, a1, 31
+; RV64I-NEXT: xor a2, a0, a1
; RV64I-NEXT: .LBB0_2:
-; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB0_3:
-; RV64I-NEXT: mv a0, a2
-; RV64I-NEXT: blt a1, a2, .LBB0_2
-; RV64I-NEXT: .LBB0_4:
-; RV64I-NEXT: lui a0, 524288
+; RV64I-NEXT: sext.w a0, a2
; RV64I-NEXT: ret
;
; RV64IZbb-LABEL: func:
diff --git a/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll b/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
index 6ff61ff415216..d113afa769931 100644
--- a/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
@@ -30,20 +30,15 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: mulw a1, a1, a2
+; RV64I-NEXT: subw a2, a0, a1
; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 524288
-; RV64I-NEXT: addiw a2, a1, -1
-; RV64I-NEXT: bge a0, a2, .LBB0_3
+; RV64I-NEXT: beq a2, a0, .LBB0_2
; RV64I-NEXT: # %bb.1:
-; RV64I-NEXT: bge a1, a0, .LBB0_4
+; RV64I-NEXT: sraiw a0, a0, 31
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB0_3:
-; RV64I-NEXT: mv a0, a2
-; RV64I-NEXT: blt a1, a2, .LBB0_2
-; RV64I-NEXT: .LBB0_4:
-; RV64I-NEXT: lui a0, 524288
-; RV64I-NEXT: ret
;
; RV64IZbb-LABEL: func32:
; RV64IZbb: # %bb.0:
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