[llvm] [RISCV] sifive-p670 uses SiFive7SchedModel (PR #80612)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Michael Maitland (michaelmaitland)

<details>
<summary>Changes</summary>

I collected numbers that show that the SiFive7SchedModel was better than using NoSchedModel.

The sifive-p670 is not a SiFive7 processor, however we have a P600SchedModel in our downstream that has not been updated since before SchedWriteRes accounted for LMUL & SEW. I collected numbers that show that the SiFive7SchedModel outpreformed this old model as well.

We intend to add the P600SchedModel in the future, once it has been revamped and causes sifive-p670 to outpreform in comparison to the SiFive7NModel.

---
Full diff: https://github.com/llvm/llvm-project/pull/80612.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 59bb811058d48..79f62465b48fb 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -245,7 +245,7 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
                                        TuneLUIADDIFusion,
                                        TuneAUIPCADDIFusion]>;
 
-def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
+def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFive7Model,
                                       [Feature64Bit,
                                        FeatureStdExtZifencei,
                                        FeatureStdExtM,

``````````

</details>


https://github.com/llvm/llvm-project/pull/80612