[llvm] [RISCV] sifive-p670 uses SiFive7SchedModel (PR #80612)

[Michael Maitland via llvm-commits]

https://github.com/michaelmaitland created https://github.com/llvm/llvm-project/pull/80612

I collected numbers that show that the SiFive7SchedModel was better than using NoSchedModel.

The sifive-p670 is not a SiFive7 processor, however we have a P600SchedModel in our downstream that has not been updated since before SchedWriteRes accounted for LMUL & SEW. I collected numbers that show that the SiFive7SchedModel outpreformed this old model as well.

We intend to add the P600SchedModel in the future, once it has been revamped and causes sifive-p670 to outpreform in comparison to the SiFive7NModel.

>From de56d56c06715cbb63bd32284eaadb628c8e2adc Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Sun, 4 Feb 2024 10:08:49 -0800
Subject: [PATCH] [RISCV] sifive-p670 uses SiFive7SchedModel

I collected numbers that show that the SiFive7SchedModel was better than
using NoSchedModel.

The sifive-p670 is not a SiFive7 processor, however we have a P600SchedModel in
our downstream that has not been updated since before SchedWriteRes accounted
for LMUL & SEW. I collected numbers that show that the SiFive7SchedModel
outpreformed this old model as well.

We intend to add the P600SchedModel in the future, once it has been revamped and
causes sifive-p670 to outpreform in comparison to the SiFive7NModel.
---
 llvm/lib/Target/RISCV/RISCVProcessors.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 59bb811058d48..79f62465b48fb 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -245,7 +245,7 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
                                        TuneLUIADDIFusion,
                                        TuneAUIPCADDIFusion]>;
 
-def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
+def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFive7Model,
                                       [Feature64Bit,
                                        FeatureStdExtZifencei,
                                        FeatureStdExtM,