[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)
Jack Styles via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 2 06:32:14 PST 2024
================
@@ -2223,6 +2223,25 @@ class TargetInstrInfo : public MCInstrInfo {
llvm_unreachable("unknown number of operands necessary");
}
+ virtual unsigned getUndefInitOpcode(unsigned RegClassID) const {
----------------
Stylie777 wrote:
Comments have been added to the functions that are added by this PR.
https://github.com/llvm/llvm-project/pull/77770
More information about the llvm-commits
mailing list