[llvm] [RISCV] Exclude X1 and X5 from register scavenging for long branch. (PR #80215)

[Philip Reames via llvm-commits]

preames wrote:

> Don't we fall back to emergency spill?

You're correct.  I didn't read far enough down in the existing code and got distracted by the /*AllowSpill=*/false bit.

https://github.com/llvm/llvm-project/pull/80215