[llvm] [RISCV] Exclude X1 and X5 from register scavenging for long branch. (PR #80215)

[Craig Topper via llvm-commits]

topperc wrote:

> > Jumps using X1 and X5 as the source are hints to the hardware to pop the return-address stack. We should avoiding using them for jumps that aren't a return or tail call.
> 
> Could we instead prefer non-X1 and non-X5 registers, then fallback to scavenging them if that's all that's available? Confusing the hardware RAS predictor seems arguably better than crashing the compiler with a scavenging failure.

Don't we fall back to emergency spill?

https://github.com/llvm/llvm-project/pull/80215