[llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

[Alexey Bataev via llvm-commits]

alexey-bataev wrote:

> Don't we need to know the exact vlen to know where register boundaries are?

I use getRegUsageForType() to get this info.

https://github.com/llvm/llvm-project/pull/80164