[llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 31 08:57:37 PST 2024

Previous message: [llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
Next message: [llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

topperc wrote:

Don't we need to know the exact vlen to know where register boundaries are?

https://github.com/llvm/llvm-project/pull/80164

Previous message: [llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
Next message: [llvm] [TTI][RISCV]Improve costs for fixed vector whole reg extract/insert. (PR #80164)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list