[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[via llvm-commits]

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@@ -2223,6 +2223,25 @@ class TargetInstrInfo : public MCInstrInfo {
     llvm_unreachable("unknown number of operands necessary");
   }
 
+  virtual unsigned getUndefInitOpcode(unsigned RegClassID) const {
+    (void)RegClassID;
+
+    llvm_unreachable("Unexpected register class.");
+  }
+
+  virtual const TargetRegisterClass *
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ostannard wrote:

`getVRLargestSuperClass`, `isVectorRegClass` and `getNoRegisterValue` are properties of registers or register classes, not instructions, so they should be in `TargetRegisterInfo`.

https://github.com/llvm/llvm-project/pull/77770